A magnetic resistance random access memory of a spin transfer torque magnetization switching type (hereinafter also referred to as a spin transfer torque magnetic random access memory (STT-MRAM) is a candidate nonvolatile memory to be used in a technology that is required to consume less power, such as a processor to be used in a handheld terminal.
A memory cell in a STT-MRAM normally includes a magnetic tunnel junction (MTJ) element that includes: a storage layer including a magnetic film that has a changeable magnetization direction; a reference layer including a magnetic film that has a fixed magnetization direction; and a nonmagnetic layer (a tunnel barrier layer, for example) interposed between the storage layer and the reference layer. The memory cell also includes a select transistor. In the MTJ element, the electrical resistance between the storage layer and the reference layer varies depending on whether the magnetization directions of the storage layer and the reference layer are in a parallel state (P), or whether the magnetization directions are in an antiparallel state (AP). The electrical resistance between the storage layer and the reference layer is low in the parallel state, and is high in the antiparallel state. One of the parallel state and the antiparallel state is associated with information “0”, and the other is associated with information “1”. When the magnetization direction of the storage layer is to be switched from the antiparallel state to the parallel state relative to the magnetization direction of the reference layer, electrons flow from the reference layer to the storage layer via the nonmagnetic layer. When the magnetization direction of the storage layer is to be switched from the parallel state to the antiparallel state relative to the magnetization direction of the reference layer, electrons flow from the storage layer to the reference layer via the nonmagnetic layer.
One of the storage layer and the reference layer is connected to one of the source and the drain of the select transistor. The other one of the storage layer and the reference layer is connected to a bit line BL. The other one of the source and the drain of the select transistor is connected to a source line SL, and the gate of the select transistor is connected to a word line WL.
In a write operation in this memory cell including the select transistor and the MTJ element, current is applied from the source line SL to the bit line BL, or current is applied from the bit line BL to the source line SL, so that the resistance state of the MTJ element is switched from a high-resistance state to a low-resistance state or from a low-resistance state to a high-resistance state, and information “0” or information “1” is recorded.
Meanwhile, in a read operation in the above described memory cell, a read current is applied from one line to the other between the source line SL and the bit line BL, or from the source line SL to the bit line BL, for example, and the resistance value of the MTJ element at that time is read through the current value or the voltage value. In an example case, the storage layer of the MTJ element is connected to the bit line BL, the reference layer is connected to one of the source and the drain of the select transistor, the other one of the source and the drain is connected to the source line SL, and the magnetization direction of the storage layer is parallel (P) to the magnetization direction of the reference layer. In this case, when the read current is applied from the source line SL to the bit line BL, the current direction is the same as that in a case where an antiparallel state (AP) is written into the storage layer, and a wrong write might be performed.
In another example case, the reference layer of the MTJ element is connected to the bit line BL, the storage layer is connected to one of the source and the drain of the select transistor, the other one of the source and the drain is connected to the source line SL, and the magnetization direction of the storage layer is antiparallel (AP) to the magnetization direction of the reference layer. In this case, when the read current is applied from the source line SL to the bit line BL, the current direction is the same as that in a case where a parallel state (P) is written into the storage layer, and a wrong write might be performed.
Such a wrong write becomes conspicuous particularly in a case where the difference in current amount between a read operation and a write operation is smaller, such as a case where the read current is increased to speed up operation or a case where an element to reduce the write current is used. As a result, such a wrong write hinders improvement in the performance of the STT-MRAM.